New Updates About St Joseph's College of Engineering & Technology, Kottayam, Kerala

About Master of Technology (M.Tech) Very Large Scale Integration (VLSI) Engineering

Program Duration
Full Time ,2 Years

Course Type
PG , Engineering

Eligibility
Atleast 55% marks in B.E. /B.Tech or equivalent in appropriate branches (50% marks for SC /ST) Read More

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Master of Technology (M.Tech) Very Large Scale Integration (VLSI) Engineering - Highlights

Particular Details
Total Seats N/A
Duration 2 Years
Accepted Exams GATE

Popular Exams

Exam Month

February

Accepting Colleges
Last Date to Apply

01st February, 2025

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Important Exam Events:

Particular Details
GATE Exam Start Date 1st February, 2025
GATE Exam Date 1st February, 2025
GATE Exam End Date 16th February, 2025

Master of Technology (M.Tech) Very Large Scale Integration (VLSI) Engineering - Eligibility

Atleast 55% marks in B.E. /B.Tech or equivalent in appropriate branches (50% marks for SC /ST)

Master of Technology (M.Tech) Very Large Scale Integration (VLSI) Engineering - Admission Process

Candidates, who have passed AMIE / AMIETE Examinations and satisfying the following conditions, are eligible for admission. 1) They must have valid GATE score. 2) A minimum of 55% marks for section B in AMIE/AMIETE examination.

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